1. Field of the Invention
The present invention relates to a multi-layer capacitor.
2. Description of the Related Art
Recent implementation of high-speed ICs in the field of information and communications technology, typified by digital circuits used in computers and radio transmission, is striking. However, such attainment of high speed and high degree of integration for ICs involves an increase in high-frequency noise, which causes equipment malfunction, and thus raises a serious problem. The high-frequency noise is caused by a drop in supply voltage resulting from simultaneous switching of logic devices. In order to reduce the high-frequency noise, a capacitor for supplying energy to a power supply, or a so-called decoupling capacitor, has been used.
In order to achieve instantaneous supply of large energy, the decoupling capacitor is required to have a large capacitance and a low inductance (ESL). These characteristics mainly depend on the internal structure of a capacitor, and various internal structures have been proposed.
In the case of handling high-frequency waves and high-speed pulses, a conductor line that connects an electronic component mounted on a wiring board to a power supply for supplying operating power to the electronic component imparts excess inductance. An increase in an inductance component of a conductor line increases the difficulty of attaining stable supply of operating voltage. Furthermore, superposition of noise on a conductor line causes malfunction of an electronic component. The above-mentioned implementation of high frequency and a high degree of circuit integration increases occurrence of such a problem. In order to shorten the length of a conductor line extending between a capacitor and a power supply for the purpose of reducing an excess inductance component, a capacitor is proposed in which electrode terminals are formed on only one main surface of a capacitor body.
Existing multi-layer capacitors of the above-mentioned type include a multi-layer capacitor as described below (refer to, for example, Japanese Patent Application Laid-Open (Kokai) No. 5-347227). The multi-layer capacitor includes a capacitor body formed by the steps of alternately laminating dielectric layers and internal electrode layers, and firing the resultant laminate. The multi-layer capacitor is characterized as follows: each of the internal electrode layers includes a first internal electrode layer and a second internal electrode layer that face each other by mediation of a dielectric layer; a first electrode terminal and a second electrode terminal are formed on one main surface of the capacitor body; a first via electrode is formed in the capacitor body so as to extend in the lamination direction of the capacitor body and to connect the first electrode terminal and the first internal electrode layers; and a second via electrode is formed in the capacitor body so as to extend in the lamination direction of the capacitor body and to connect the second electrode terminal and the second internal electrode layers. The facing first and second internal electrode layers function as a capacitor unit, which is the minimum unit that forms a capacitance. The capacitor units are connected in parallel by the first and second via electrodes.
Another known mode of the above-described multi-layer capacitor includes a plurality of first and second via electrodes and a plurality of first and second electrode terminals corresponding to the via electrodes, the plurality of first and second via electrodes being arrayed in a grid.
Recent implementation of ICs (integrated circuits) of high speed and high degree of integration requires a further reduction in the ESL (equivalent series resistance) of a capacitor and reduction in size with high electrical and mechanical reliability without involving a reduction in the capacitance thereof.